The present invention relates to a semiconductor memory and a method of manufacturing the same and, more particularly, to a semiconductor memory which can sufficiently achieve an electrical connection between a charge storage conductor for a capacitor and an impurity diffusion layer of a MOS transistor in a dynamic memory call consisting of a MOS transistor and a capacitor, and a method of manufacturing a semiconductor memory which does not require a mask alignment margin when a charge storage conductor is electrically connected to an impurity diffusion layer.
One MOS transistor for a transfer gate and one capacitor for charge storage have been conventionally used as a memory cell of a DRAM (a dynamic random access memory). A planar type capacitor, a stacked type capacitor, a trench type capacitor, or the like is used as the capacitor. In FIG. 1, one example called as buried stacked type capacitor is shown. Referring to FIG. 1, reference numeral 41 denotes a semiconductor substrate; 42, a field oxide film; 43, a trench formed in a part of an element formation region; 44, a first insulating film formed on the surface of the trench; 45, a capacitor charge storage layer formed on the first insulating film; 46, a capacitor insulating film formed on the charge storage layer 45; and 47, a capacitor electrode conductor formed on the capacitor insulating film 46. The conductor 47 is partially buried in the trench 43. Reference numeral 48 denotes a MOS transistor gate insulating film formed on a part of the element formation region of the substrate 41; 49, a gate electrode; and 50 and 51, impurity diffusion layers for source and drain regions formed in the surface of the substrate 41. In order to electrically connect the MOS transistor impurity diffusion layer 51 to the capacitor charge storage layer 45, a window 53 is formed in a part of the insulating film 44 on the surface of the substrate 41 by mask alignment etching. An impurity is diffused in the substrate 41 from the charge storage layer 45 through the window 53 to form a conductive layer 56. Thus, the impurity diffusion layer 51 is electrically connected to the charge storage layer 45 through the conductive layer 56. Note that reference numeral 54 denotes an interlayer insulating film; and 55, a bit line wiring layer.
As described above, however, when the insulating film 44 for preventing short-circuiting between the semiconductor substrate 41 and the charge storage layer 45 is partially opened to form the window 53 by mask alignment etching, a margin a must be formed to prevent misalignment between the window 53 and the charge storage layer 45. Furthermore, a margin b must be formed to prevent misalignment between the window 53 and the trench 43. For this reason, a memory cell area is undesirably increased by these margins a and b, and hence the integration degree of the memory cell cannot be increased. When the mask misalignment is large upon formation of the window 53, offset occurs between the conductive layer 56 formed by impurity diffusion through the window 53 and the impurity diffusion layer 51 of the transistor. As a result, the electrical connection between the two layers may not be sufficiently achieved.
On the other hand, in order to miniaturize a MOS transistor, an integrated circuit in which a source or drain region impurity diffusion layer on the substrate surface is connected to first and second polysilicon layers on the substrate through one contact opening via aluminum wiring is disclosed in Japanese Patent Disclosure (Kokai) No. 58-215055. A wiring contact structure in which an impurity diffusion layer on the substrate surface is connected to a first polysilicon semiconductor layer on the substrate through a second polysilicon semiconductor layer is disclosed in Japanese Patent Disclosure (Kokai) No. 54-40580.
The above disclosures do not disclose a manufacturing method for a miniaturizing a dynamic memory cell while the insulation between a capacitor charge storage layer and a capacitor electrode conductor is assured.